The invention relates to a DRAM cell configuration, i.e. a dynamic random access memory cell configuration, in which bit lines are buried in a substrate, and to a method of fabricating the DRAM cell configuration.
At present, DRAM cell configurations are formed with memory cells that are almost exclusively so-called one-transistor memory cells. Those cells each comprise one transistor and one capacitor. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, with the result that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
It is generally endeavored to produce a DRAM cell configuration with high packing density.
U.S. Pat. No. 5,497,017 describes a DRAM cell configuration comprising one-transistor memory cells. A space requirement per memory cell may be 4F2, where F is the minimum feature size that can be fabricated in the technology used. In order to produce bit lines, trenches running parallel to one another are etched in a silicon substrate. A thin insulating layer is deposited which does not fill the trenches. In order to produce the bit lines, the trenches are filled with tungsten. The insulating layer is in each case removed from a side wall of each trench, with the result that the bit lines are partly uncovered laterally. Source/drain regions and channel regions of vertical transistors are produced by epitaxy. In this case, lower source/drain regions of the transistors laterally adjoin the bit lines. Word lines run transversely with respect to the bit lines and in trenches, which are arranged between mutually adjacent transistors.
It is accordingly an object of the invention to provide a DRAM cell configuration whose memory cells each have a transistor and a capacitor, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and the bit lines of which are buried in the substrate and which can be fabricated with a space requirement per memory cell of 4F2 and, at the same time, with lower process complexity by comparison with the prior art. Furthermore, it is an object of the invention to provide a fabrication method for producing the novel DRAM cell configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising:
a plurality of memory cells each having a vertical transistor and a capacitor;
a substrate formed with substantially parallel trenches each having side walls and having a bit line arranged therein in a lower part thereof;
an insulation formed in the lower part of a respective said trench between said bit line and said substrate, except for a strip-type cut-out formed parallel to said trench and in said first sidewall of said trench;
a further insulation formed on parts of said side walls of said trench above the lower part of said trench and an upper area of said bit line;
word lines extending transversely with respect to said bit line, said word lines, except for downwardly directed protuberances that reach into said trenches and that are arranged above said bit lines, running above said substrate, and an insulating layer isolating said word lines from said substrate;
said protuberances of said word lines and insulating structures being arranged alternately above said bit line in said trench;
said transistors having upper source/drain regions and lower source/drain regions arranged between said trenches and under said word lines;
further insulating structures formed in said substrate for insulating from one another upper source/drain regions of mutually adjacent transistors along said trench; and
wherein said upper source/drain regions of said transistors are connected to said capacitors of said memory cells.
In other words, the problems underlying the invention are solved by means of a DRAM cell configuration having memory cells which each have a transistor and a capacitor, in which a substrate has trenches which essentially run parallel to one another and in each of which a bit line is arranged. The bit line is arranged in a lower part of the associated trench. The lower part of the trench, except for a strip-type cut-out which runs parallel to the trench and is arranged on a first side wall of the trench, is provided with an insulation, which is arranged between the bit line and the substrate. Parts of the side walls of the trench which are arranged above the lower part of the trench and an upper area of the bit line are provided with a further insulation. Word lines run transversely with respect to the bit line. The word lines, except for downwardly directed protuberances, which reach into the trenches and are arranged above the bit lines, run above the substrate. Insulating structures and the protuberances of the word lines are arranged alternately in the trench above the bit lines. The transistors of the memory cells are configured as vertical transistors. Upper source/drain regions and lower source/drain regions of the transistors are arranged between the trenches. Further insulating structures are arranged in the substrate, which structures isolate from one another upper source/drain regions of mutually adjacent transistors along the trench. The upper source/drain regions of the transistors are connected to the capacitors of the memory cells.
The protuberances of the word lines act as gate electrodes of the transistors.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating a DRAM cell configuration. The method comprises the following method steps:
producing an insulating layer on a substrate;
forming substantially parallel trenches in the substrate;
providing an insulation for lower parts of the trenches, except for strip-type cut-outs running parallel to the trenches and arranged on first side walls of the trenches;
producing a bit line in each trench in a lower part thereof;
providing a further insulation for parts of the side walls of the trenches arranged above the lower parts of the trenches and for the bit lines;
filling the trenches with a conductive material;
covering the conductive material with a protective layer;
patterning the conductive material and the protective layer to produce word lines covered by the protective layer and running transversely with respect to the bit lines and having downwardly directed protuberances reaching into the trenches;
depositing insulating material and etching the insulating material back together with the insulating layer selectively with respect to the protective layer and with respect to the substrate, until the substrate is uncovered, such that insulating structures are produced in the trenches, between the protuberances of the word lines and above the bit lines;
etching the substrate selectively with respect to the insulating structures to produce depressions between the word lines and between the trenches;
producing upper source/drain regions of transistors of memory cells between the trenches and between the depressions in the substrate;
producing lower source/drain regions of the transistors each adjoining one of the cut-outs, in the substrate under the upper source/drain regions;
producing further insulating structures in the depressions; and
producing capacitors of the memory cells and connecting each of the capacitors to one of the upper source/drain regions.
In other words, the problems underlying the invention are furthermore solved by means of a method for fabricating a DRAM cell configuration having memory cells which each have a transistor and a capacitor, in which an insulating layer is produced on a substrate. Trenches, which essentially run parallel to one another are produced in the substrate. Lower parts of the trenches, except for strip-type cut-outs which run parallel to the trenches and are arranged on first side walls of the trenches, are provided with an insulation. A bit line is in each case produced in the lower parts of the trenches. Parts of the side walls of the trenches which are arranged above the lower parts of the trenches and the bit lines are provided with a further insulation. Conductive material is applied, the trenches thereby being filled. A protective layer is produced, which covers the conductive material. The conductive material and the protective layer are patterned in such a way that word lines covered by the protective layer are produced, which word lines run transversely with respect to the bit lines and have downwardly directed protuberances which reach into the trenches. Insulating material is deposited and etched back together with the insulating layer selectively with respect to the protective layer and with respect to the substrate, until the substrate is uncovered, with the result that insulating structures are produced in the trenches, which structures are arranged between the protuberances of the word lines and above the bit lines. The substrate is etched selectively with respect to the insulating structures, with the result that depressions are produced between the word lines and between the trenches. Upper source/drain regions of transistors of memory cells are produced between the trenches and between the depressions in the substrate. Lower source/drain regions of the transistors, which in each case adjoin one of the cut-outs, are produced in the substrate under the upper source/drain regions. Further insulating structures are produced in the depressions. Capacitors of the memory cells are produced, which are in each case connected to one of the upper source/drain regions. On the first side walls of the trenches, the word lines act as gate electrodes of the transistors and the further insulation acts as a gate dielectric.
No epitaxy is required for producing the source/drain regions of the transistors. This means that the process is simplified.
The upper source/drain regions, the lower source/drain regions, the insulating structures and the further insulating structures are produced in a self-aligned manner with respect to the word lines and with respect to the trenches, with the result that the DRAM cell configuration can have a high packing density, i.e. a small space requirement per memory cell. If the trenches are produced with a strip-type mask whose strips run parallel to one another and the word lines are patterned with the aid of a further strip-type mask whose strips run parallel to one another and transversely with respect to the trenches, and if the strips have a width of F and a spacing of F from one another, then the space requirement of a memory cell can be 4F2, where F is the minimum feature size that can be fabricated in the technology used.
In order to avoid floating body effects, it is advantageous if the lower source/drain region of a transistor is arranged between the trench and an adjacent trench and is spaced apart from the adjacent trench. In this case, a channel region of the transistor, which is arranged between the lower source/drain region and the upper source/drain region, is electrically connected to the largest part of the substrate.
In order to produce such a lower source/drain region, at least a part of the bit line which adjoins the cut-out may be composed of doped polysilicon. During a heat treatment step, dopant diffuses from the bit line into the substrate, where it forms a doped region which is arranged between the trench and the adjacent trench, adjoins the cut-out and is spaced apart from the adjacent trench. This heat treatment step may be, for example, a thermal oxidation for producing a gate dielectric.
Parts of the doped region, which are arranged under the upper source/drain regions act as the lower source/drain regions.
The doped region can be patterned by the depressions, with the result that the lower source/drain regions of mutually adjacent transistors along the trench, which are isolated from one another, are produced from the doped region. In this case, the lower source/drain regions of the mutually adjacent transistors along the trench and the further insulating structures alternately adjoin the bit line in the region of the cut-out.
As an alternative, the lower source/drain region is produced by patterning a lower doped layer of the substrate. The patterning is effected by the production of the trenches. In order to isolate from one another lower source/drain regions of the mutually adjacent transistors along the trench, it is possible, in this case, too, for the depressions to be produced in such a way that they reach more deeply than the cut-outs of the insulation.
The upper source/drain region can be produced by patterning an upper doped layer of the substrate. The patterning is effected by the production of the depressions and of the trenches. The depressions are thus at least deep enough that they cut through the upper doped layer.
The upper source/drain region can also be produced by implantation. By way of example, the implantation is effected after the production of the trenches. The upper source/drain regions of transistors, which are adjacent to one another along the bit line are isolated from one another by the production of the depressions.
The connection of the capacitor to the upper source/drain region can be effected via a conductive structure. To that end, the upper source/drain region of the transistor is covered with an insulating layer. The word line runs above the insulating layer. A projection of the upper source/drain region onto the insulating layer overlaps a projection of the word line onto the insulating layer in such a way that it is extended beyond two sides of the projection of the word line, with the result that projections of two parts of the upper source/drain region adjoin the projection of the word line and do not overlap the projection of the word line. Consequently, transversely with respect to the word line, the upper source/drain region has a larger dimension than the word line. Side walls of the word line are provided with insulating spacers. An upper surface of the word line, which surface is remote from the upper source/drain region, is provided with an insulating protective layer. A conductive structure covers the protective layer and the spacers and overlaps the two parts of the upper source/drain region. The capacitor is arranged on the conductive structure.
The conductive structure can be produced in a self-aligned manner with respect to the word line and does not increase the space requirement of the memory cell. By way of example, the spacers are produced before the production of the depressions by depositing and etching back insulating material. After the production of the insulating structures, conductive material is deposited to a thickness such that interspaces between the word lines are not filled. A mask is produced, which covers horizontal surfaces of parts of the conductive material, which are arranged above the word line. The conductive material and the substrate are etched selectively with respect to the mask. Parts of the conductive material, which are arranged between the word lines are consequently removed. In the process, the conductive structures are produced from the conductive material, and the depressions are produced in the substrate.
The mask can be produced in a self-aligned manner, with the result that the space requirement of the memory cell is not increased.
One possibility for producing the mask consists in depositing insulating material non-conformally, with the result that the insulating material is thickest above the horizontal surfaces of those parts of the conductive material, which are arranged above the word line. The mask is produced from the insulating material by etching back the insulating material until parts of the conductive material, which are arranged between the word lines are uncovered. In this case, the mask covers not only the horizontal surfaces of those parts of the conductive material which are arranged above the word line, but also areas of the conductive material which run transversely with respect thereto.
A further possibility for producing the mask consists first of all in depositing the conductive material, which contains doped polysilicon, and then depositing an auxiliary material and etching it back until lateral areas of the conductive material are partly uncovered. Afterward, a thermal oxidation is carried out, thereby producing the mask on uncovered parts of the conductive material. The auxiliary material is subsequently removed.
In order to increase the electrical conductivity of the bit line, the latter may be partly composed of metal. In addition to molybdenum or tantalum, tungsten is partly suitable if the substrate is composed of silicon, since silicon and tungsten have approximately the same thermal expansion coefficients, thereby avoiding mechanical strain and defects resulting therefrom in the event of temperature changes.
In order to prevent the situation where a metal silicide, which has a lower electrical conductivity, is formed, on account of diffusion, from the metal of the bit line and the silicon of the substrate or, if provided, the polysilicon of the bit line, it is advantageous to provide a diffusion barrier between the metal and the silicon or the polysilicon. By way of example, a lower part of the bit line is composed of metal. Arranged above it there is a diffusion barrier containing nitrogen. The polysilicon which adjoins the cut-out is arranged on the diffusion barrier.
In order to avoid leakage currents on account of high electric fields at edges of the word lines, it is advantageous to carry out a thermal oxidation after the production of the word lines, with the result that those parts of the further insulations, which are covered by the word lines are thickened at the edges of the word lines.
In order to increase the electrical conductivity of the word lines, the word lines may comprise two parts. A lower part of the word lines, which comprises the protuberances, is preferably composed of doped polysilicon. The second parts of the word lines, which are arranged above the first parts, may be composed e.g. of a metal silicide, such as tungsten silicide. The word lines may also comprise doped polysilicon, an e.g. nitrogen-containing diffusion barrier arranged above the latter, and metal, e.g. tungsten, arranged above the latter.
The insulating layer, the insulation, the further insulation, the insulating structures, the further insulating structures and the mask are composed, for example, of SiO2 or of silicon nitride. However, other insulating materials also lie within the scope of the invention.
The same applies to the protective layer and the spacers. If the insulating layer is composed of SiO2, for example, then the protective layer is preferably composed of silicon nitride in order to enable selective etching.
Instead of silicon, the substrate may be composed of another material, which is suitable for transistors. By way of example, the substrate may contain GaAs.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a DRAM cell configuration and a corresponding fabrication method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.